1. Field of the Invention
This invention relates to a driving apparatus for driving a pixel.
2. Description of the Related Art
FIG. 1 shows an example of a configuration of a pixel driving circuit or V driving circuit of a CMOS (Complementary Metal Oxide Semiconductor) image sensor and particular shows a portion of a pixel driving circuit or V driving circuit wherein pixels in an nth row are driven for the convenience of illustration. Further, while, in FIG. 1, an AND circuit, an OR circuit and a NOT circuit are used for simplified description, an actual circuit is implemented not using AND, OR and NOT circuits but using NAND, NOR and NOT circuits.
Referring to FIG. 1, the pixel driving circuit 10 shown includes an address decoder 11, a timing adjustment section 12, a driver section 13 and a control section 14, and produces and outputs a transfer gate signal TR(n), a reset signal RST(n) and a select signal SEL(n) for driving the pixels in the nth row.
The address decoder 11 supplies a row selection signal φV_LINE(n) for selecting the pixels in the nth row as a driving target to the timing adjustment section 12 at a predetermined timing.
The timing adjustment section 12 adjusts the timing of production of the transfer gate signal TR(n), reset signal RST(n) and select signal SEL(n). In particular, the timing adjustment section 12 includes AND circuits 21 and 22, an OR circuit 23 and a NOT circuit 24 which cooperate to function as a logic gate circuit for adjusting the timing of production of the transfer gate signal TR(n). The timing adjustment section 12 further includes an AND circuit 25 and a NOT circuit 26 which cooperatively function as a logic gate circuit for adjusting the timing of production of the reset signal RST(n). The timing adjustment section 12 further includes an AND circuit 27 and a NOT circuit 28 which cooperatively function as a logic gate circuit for adjusting the timing of production of the select signal SEL(n).
The AND circuit 21 logically ANDs the row selection signal φV_LINE(n) inputted from the address decoder 11 and a timing signal φRTR inputted from the control section 14 and supplies a signal obtained by the logical ANDing to the OR circuit 23. The AND circuit 22 logically ANDs the row selection signal φV_LINE(n) inputted from the address decoder 11 and another timing signal φSTR inputted from the control section 14 and supplies a signal obtained by the logical ANDing to the OR circuit 23.
The OR circuit 23 logically ORs the signal supplied from the AND circuit 21 and the signal supplied from the AND circuit 22 and supplies a signal obtained by the logical ORing to the NOT circuit 24. The NOT circuit 24 operates logical negation of the signal supplied from the OR circuit 23 and supplies a signal obtained by the logical negation to the driver section 13. Consequently, the timing of production of the transfer gate signal TR(n) to be produced by the driver section 13 hereinafter described is controlled.
The AND circuit 25 logically ANDs the row selection signal φV_LINE(n) inputted from the address decoder 11 and a timing signal φRST inputted from the control section 14 and supplies a signal obtained by the logical ANDing to the NOT circuit 26. The NOT circuit 26 operates logical negation of the signal supplied from the AND circuit 25 and supplies a signal obtained by the logical negation to the driver section 13. As a result, the timing of production of the reset signal RST(n) to be produced by the driver section 13 is controlled.
The AND circuit 27 logically ANDs the row selection signal φV_LINE(n) inputted from the address decoder 11 and a timing signal φSEL inputted from the control section 14 and supplies a signal obtained by the logical ANDing to the NOT circuit 28. The NOT circuit 28 operates logical negation of the signal supplied from the AND circuit 27 and supplies a signal obtained by the logical negation to the driver section 13. Consequently, the timing of production of the select signal SEL(n) to be produced by the driver section 13 is controlled.
The driver section 13 produces and outputs the transfer gate signal TR(n), reset signal RST(n) and select signal SEL(n) in accordance with the signals supplied from the timing adjustment section 12.
In particular, in the driver section 13, a pMOS transistor 31 and an nMOS transistor 32 are connected in series. A potential VDD is connected as a potential of the high level to the source of the pMOS transistor 31, and a potential VSS is connected as a potential of the low level to the source of the nMOS transistor 32. A signal supplied from the NOT circuit 24 of the timing adjustment section 12 is supplied to the gate of the pMOS transistor 31 and the nMOS transistor 32. If the signal is a low-level signal, then the pMOS transistor 31 is placed into an on state, but if the signal is a high-level signal, then the nMOS transistor 32 is placed into an on state.
As a result, if the signal inputted to the gate is a low-level signal, then the potential at a point at which the drains of the pMOS transistor 31 and the nMOS transistor 32 are connected to each other becomes the potential VDD, but, if the signal inputted to the gate is a high-level signal, then the potential at the point becomes the potential VSS. The point mentioned is hereinafter referred to as transfer gate junction point. Then, a signal of the potential is applied as the transfer gate signal TR(n) to the transfer gate of the pixels in the nth row of a pixel section which is formed from a plurality of pixels. In this manner, the driver section 13 produces and outputs the transfer gate signal TR(n) in accordance with the signal supplied from the timing adjustment section 12.
Further, in the driver section 13, a PMOS transistor 33 and an nMOS transistor 34 are connected in series similarly to the pMOS transistor 31 and the nMOS transistor 32, and the potentials VDD and VSS are connected to the sources of the pMOS transistor 33 and the nMOS transistor 34, respectively. A signal supplied from the NOT circuit 26 of the timing adjustment section 12 is supplied to the gate of the pMOS transistor 33 and the nMOS transistor 34. Then, a signal of the potential at a point at which the drains of the pMOS transistor 33 and nMOS transistor 34 are connected to each other is inputted as the reset signal RST(n) to the pixels in the nth row of the pixel section. The point mentioned is hereinafter referred to as reset junction point. As a result, the reset signal RST(n) of the potential VDD or the potential VSS is inputted to the pixels in the nth row of the pixel section in accordance with the signal supplied from the timing adjustment section 12.
Furthermore, in the driver section 13, a pMOS transistor 35 and an nMOS transistor 36 are connected in series similarly to the pMOS transistor 31 and the nMOS transistor 32, and the potentials VDD and VSS are connected to the sources of the pMOS transistor 35 and the nMOS transistor 36, respectively. A signal supplied from the NOT circuit 28 of the timing adjustment section 12 is supplied to the gate of the pMOS transistor 35 and nMOS transistor 36. Then, a signal of the potential at a point at which the drains of the pMOS transistor 35 and the nMOS transistor 36 are connected to each other is inputted as the select signal SEL(n) to the pixels in the nth row of the pixel section. The point mentioned is hereinafter referred to as select junction point. As a result, the select signal SEL(n) of the potential VDD or the potential VSS is inputted to the pixels in the nth row of the pixel section in accordance with the signal supplied from the timing adjustment section 12.
The control section 14 produces the timing signals φSEL, φRST, φSTR and φRTR of the high level or the low level at predetermined timings and supplies the produced signals to the timing adjustment section 12.
Next, timings of signals relating to the output of the transfer gate signal TR(n) in the pixel driving circuit 10 in FIG. 1 is described with reference to FIG. 2.
If the level of the row selection signal φV_LINE(n) changes from the low level to the high level at time t1 and then the level of the timing signal φSTR or the timing signal φRTR changes from the low level to the high level at time t2, then the levels of the signals produced by the AND circuits 21 and 22, OR circuit 23 and NOT circuit 24 become the low level. Accordingly, the pMOS transistor 31 is placed into an on state and the nMOS transistor 32 is placed into an off state, and the transfer gate signal TR(n) of the potential VDD is outputted to the pixel section as seen in FIG. 2.
Then, if the level of the timing signal φSTR or the timing signal φRTR changes from the high level to the low level at time t3 as seen in FIG. 2, then the levels of the signals produced by the AND circuits 21 and 22, OR circuit 23 and NOT circuit 24 become the high level. Accordingly, the PMOS transistor 31 is placed into an off state and the nMOS transistor 32 is placed into an on state, and the transfer gate signal TR(n) of the potential VSS is outputted to the pixel section as seen in FIG. 2.
Thereafter, although the level of the row selection signal φV_LINE(n) changes from the high level to the low level at time t4 as seen in FIG. 2, the level of the signals produced by the AND circuits 21 and 22, OR circuit 23 and NOT circuit 24 is maintained at the high level. Accordingly, the transfer gate signal TR(n) of the potential VSS continues to be outputted to the pixel section as seen in FIG. 2.
It is to be noted that, while it is described above that the timing signal φSTR or the timing signal φRTR has the high level or else the low level, this description signifies both of a case wherein both of the timing signals φSTR and φRTR have the high level or the low level and another case wherein one of the timing signals φSTR and φRTR has the high level or the low level while the other one of the signals typically has the low level.
Further, though not shown, in the pixel driving circuit 10 shown in FIG. 1, also the potentials of the reset signal RST(n) and the select signal SEL(n) change to the potential VDD or the potential VSS in accordance with the level of the row selection signal φV_LINE(n) and the timing signal φSEL or the timing signal φRST similarly to the transfer gate signal TR(n).
Incidentally, in the pixel driving circuit 10 shown in FIG. 1, it is preferable to propagate the same signal inputted to the gate of the pMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 connected in series ideally at the completely same timing. However, there is the possibility that, upon changeover between on and off states of the pMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36, the operation timings of them may be displaced from each other such that a moment occurs at which both of the PMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 are placed into an on state.
Meanwhile, a driving circuit which outputs three values such as high, middle and low levels as such a transfer gate signal TR(n) as described above depending upon a characteristic of a pixel is known and disclosed, for example, in Japanese Patent Laid-Open No. 2002-77730. Particularly in such a driving circuit of the type as described, the number of logic gates at the preceding stage of a pMOS transistor of a driver section and the number of logic gates at the preceding stage of an nMOS transistor of the driver section are frequently different from each other. Therefore, the possibility is high that some skew deviation may appear.
Further, the pMOS transistor 31, 33 or 35 and nMOS transistor 32, 34 or 36 of the driver section 13 of the pixel driving circuit 10 are designed normally using transistors having a high capacity in order to open and close the gate of pixels for one row at the same time. Therefore, there is the possibility that, if the operation timings of the pMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 of the driver section 13 are displaced from each other such that a moment occurs at which both of the pMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 are placed into an on state, then excessively high feedthrough current may flow from the potential VDD to the potential VSS.
Then, if high feedthrough current flows to the power supply of the low level of the potential VSS and this causes the low level to fluctuate, also the low level for pressing down the gate of pixels, for example, in a different row during a storage period fluctuates. Particularly where the negative potential generated by a charge pump incorporated in a chip in which the pixel driving circuit 10 is provided is determined as the potential VSS of the low level, there is the possibility that, depending upon the capacity of the charge pump, much time may be entailed until fluctuation of the negative potential by the feedthrough current is settled. As a result, a harmful influence appears on the picture quality to degrade the picture quality.